OPTIMIZING FPGA RESOURCE ALLOCATION FOR SHA-3 USING DSP48 AND PIPELINING TECHNIQUES

Deploying SHA-3 on FPGA devices requires significant resource allocation; however, the resulting throughput still needs improvement. This study employs the DSP48 module on the Xilinx FPGA to address this issue and implements an eight-stage pipeline methodology to minimize latency. The implementation design comprises a datapath and controller module, utilizing a Xilinx Artix-7-100T series FPGA as the hardware. This method makes use of FPGA resources like Look-Up Tables (LUT), Look-Up Table Random Access Memory (LUTRAM), Flip-Flops (FF), Block RAM (BRAM), Digital Signal Processing (DSP), Input/Output (IO), and Buffer (BUFG). The system’s highest frequency is 107.979 MHz, achieving different throughputs for cryptographic hash functions. Specifically, it performs a throughput of 5.183 Gbps for SHA3-224, 4.895 Gbps for SHA3-256, 3.743 Gbps for SHA3-384, and 2.591 Gbps for SHA3-512.