A simple cache coherence scheme for integrated CPU-GPU systems

Yudha, Ardhi Wiratama Baskara and Pulungan, Reza and Hoffmann, Henry and Solihin, Yan (2020) A simple cache coherence scheme for integrated CPU-GPU systems. In: 2020 57th ACM/IEEE Design Automation Conference (DAC), 20-24 July 2020, San Francisco, CA, USA.

Full text not available from this repository. (Request a copy)

Abstract

This paper presents a novel approach to accelerate applications running on integrated CPU-GPU systems. Many integrated CPU-GPU systems use cache-coherent shared memory to communicate. For example, after CPU produces data for GPU, the GPU may pull the data into its cache when it accesses the data. In such a pull-based approach, data resides in a shared cache until the GPU accesses it, resulting in long load latency on a first GPU access to a cache line. In this work, we propose a new, push-based, coherence mechanism that explicitly exploits the CPU and GPU producer-consumer relationship by automatically moving data from CPU to GPU last-level cache. The proposed mechanism results in a dramatic reduction of the GPU L2 cache miss rate in general, and a consequent increase in overall performance. Our experiments show that the proposed scheme can increase performance by up to 37, with typical improvements in the 5-7 range. We find that even when tested applications do not benefit from the proposed approach, their performance does not decrease with our technique. While we demonstrate how the proposed scheme can co-exist with traditional cache coherence mechanisms, we argue that it could also be used as a simpler replacement for existing protocols. © 2020 IEEE.

Item Type: Conference or Workshop Item (Paper)
Additional Information: Cited by: 3; Conference name: 57th ACM/IEEE Design Automation Conference, DAC 2020; Conference date: 20 July 2020 through 24 July 2020; Conference code: 163890
Uncontrolled Keywords: Computer aided design; Graphics processing unit; Cache Coherence; L2 Cache; Last-level caches; Push-based; Shared cache; Shared memory; Simple cache coherences; Cache memory
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Divisions: Faculty of Mathematics and Natural Sciences > Computer Science & Electronics Department
Depositing User: Sri JUNANDI
Date Deposited: 15 Aug 2025 09:15
Last Modified: 15 Aug 2025 09:15
URI: https://ir.lib.ugm.ac.id/id/eprint/16847

Actions (login required)

View Item
View Item