Busbar Study Regarding Stray Inductance of a 50kW 600V Three-Phase Static Inverter for Railway Applications

Static inverter in railway applications converts DC voltages into static AC voltages to supply auxiliary load inside a train. As demand increases, a higher power density inverter is needed. On the other hand, a compact inverter is an important requirement to suppress the overall production and fuel cost. Thus, a high-frequency switching technique is implemented, and SiC MOSFET with a 1.2 kV rating is chosen to achieve high power-high frequency applications. With high-power density, oscillation or spike voltages problem because of stray inductances need to be addressed carefully. This paper discusses a laminated busbar modeling of a 50 kW 600 V 3-phase static inverter through LTSpice simulation. Using a 40 kHz switching frequency, the laminated busbar with a total stray inductance of 35.23 nH has a 35% voltage ripple across MOSFET and a 13% voltage ripple on the dc-link capacitor bus. It reduces the voltage stress on MOSFET by about 33% from 1.2 kV to 810 V and reduces the dc-link bus voltage by about 25% from 950 V to 680 V compared to a conventional busbar. Hence, the simulation results ensure safe operational performance for the static inverter.